MP6903 fast turn-off intelligent controller MP6903 rev. 1. 04 www.monolithicpower.com 1 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology descri ption the MP6903 is a low-d r op diode e m ulator that, combined with an external switch, replaces schottky diodes in high-efficiency llc converters. the chip re gulates the f o rward drop of an external switch to about 70mv and switches it off as soon as the voltage goes negative. MP6903 has a light- l oad sleep mode that reduces the quiesce nt current to < 300a. features ? works with standard and logic-level fets ? compatible with energy star, 1w standby requiremen ts ? v dd range f r om 8v to 2 4 v ? fast turn-off: total delay of 20ns ? max 400khz switching f r equency ? <300a qui e scent current in light load mode ? supports dcm, ccm a nd crcm operation ? supports high-side and low-side rectification ? power savi ngs of up to 1.5w for a typical notebook adapter appli c ations ? industrial po wer syste m s ? distributed power systems ? battery powered systems ? llc converters all mp s pa r t s ar e l e ad- fre e and a d h e r e to th e r o hs d i r e ctiv e. fo r m p s g r e e n st atus, p l e a se vi si t mp s we bs ite un d er pro d u cts, q u a l it y ass u r a nce pa ge . ?mp s ? an d ?t he f u ture o f ana l o g ic t e chno lo gy ? ar e re gi ste r ed tr ade ma r ks o f monolithic power systems, inc. typical application r1 q2 ou tput 8 m p 69 03 pg n d en ll v d v g nc v dd v ss 7 6 5 4 3 2 1 gn d vg1 vg 1 out p u t u1 vg 2 en vg 2 8 m p 69 03 pg n d en ll v d v g nc v dd v ss 7 6 5 4 3 2 1 u2 en c1 c2 r2 r 3 c3 c4 r4 or l e f t op e n 2. 2 u f 10 0 k 1n f 1 00k 1n f 12 0 k 10 k r5 r6 1k 1k q1 qa q b l s c s l m c in http://
MP6903- f a st turn-off intel l igent controll er MP6903 rev. 1. 04 www.monolithicpower.com 2 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. ordering information part number* package top marking MP6903ds soic8 MP6903 * for tap e & reel, ad d suf f ix ?z (e.g. MP6903 ds?z ); for rohs co mpliant packaging, ad d su ffix ?lf (e.g. MP6903 ds? l f?z ) package reference pgnd en ll v d v g nc v dd v ss 1 2 3 4 8 7 6 5 t op view absolute m a xi mum ratings (1) v dd to v ss ...................................... -0.3v to +27v pgnd to v ss ................................ -0.3v to +0.3v v g to v ss ......................................... -0.3v to v dd v d to v ss ..................................... -0.7v to +180v ll, en to v ss ............................... -0.3v to +6.5v maxi mum operating fre quency............. 400khz continuous power dissipation (t a =25c) (2) ............................................................. 1.4w junction te mperature ............................... 150c lead temperature (solder)....................... 260c storage temperature .............. -55c to +150c recommended operation conditions (3) v dd to v ss ............................................ 8v to 24v operating junction temp. (t j ) . ... -40c to +125c thermal resistance (4) ja jc soic8 ..................................... 90 ...... 45 ... c/w notes : 1) exceeding these ratings ma y da m age the device. 2) the ma ximum allowable po w e r dissipation is a fun c tion of the maximum junction tempe r ature t j (max), the junction-to- ambient therm a l resistance ja , a nd the a m bient t e mperatu r e t a . the ma ximu m allow able cont inuous po w e r di ssipation at an y ambient tem peratur e is calculated b y p d (max)=(t j (max)- t a )/ ja . exceedi ng the m a ximum allow a ble po w e r dissipation w ill cause ex cessive die temperature, and the reg u l ator w ill go into thermal sh utdo w n . inte rnal thermal shutdo w n circuitr y protects the device from perma ne nt damage. 3) the device is not guarant eed to function outside of its operating conditions. 4) measured on je sd51-7, 4 - la y e r pcb.
MP6903- f a st turn-off intel l igent controll er MP6903 rev. 1. 04 www.monolithicpower.com 3 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. electri c al characteristi cs v dd = 12v, -40c t j 1 25c, unless otherw i se noted. parameter sy mbol conditio ns min t y p max u nits v dd voltage ran ge 8 24 v v dd uvlo ri sing 4.8 6.0 7.0 v v dd uvlo hystere s i s 0.8 1 1.2 v operating cu rre nt i cc c load =5nf, f sw =100kh z 8 10 ma quie scent current i q v ss -v d =0. 5 v 2 3 ma v dd =4v 190 260 shutdown cu rre nt v dd =20v, en=0v 350 420 a light-l oad m ode current 290 400 a therm a l shut down (5) 170 180 190 c therm a l shut down hyste r e s is (5) 30 40 50 c enable uv lo risin g 1.1 1.5 1.9 v enable uv lo hysteresi s 0.2 0.4 v internal pull-up cu rrent on en pin 10 15 a control circuitry section v ss ?v d forward voltag e v fwd 55 70 85 mv -20 c t j 125c 250 380 t don c load = 5nf -40 c t j <-20 c 650 ns -20 c t j 125c 400 680 turn -on d e la y t don c load = 10nf -40 c t j <-20 c 1200 ns input bias cu rre nt on v d pin v d = 180v 0.5 3 a minimum on-time t mi n c load = 5nf 0.4 0.8 1.2 s light-l oad -e nter del a y t ll-del a y r ll =10 0 k ? 80 120 150 s light-l oad -e nter pulse wi dth t ll r ll =10 0 k ? 1.3 1.75 2.2 s light-l oad -e nter pulse wi dth hysteresi s t ll-h r ll =10 0 k ? 0.2 s light-l oad resi stor valu e r ll 30 300 k ? light-l oad m ode exit pulse width th re sh old (v ds ) v ll-ds -400 -250 -150 mv light-l oad m ode enter pul s e width th re sh old (v gs ) (5) v ll-gs 1.0 v gate driver section v g (low) i load =1ma 0.05 0.1 v v dd >17v 13 14.5 16 v v g (high ) v dd <17v v dd -2.2 turn off thre shol d (v ss -v d ) (5) 0 30 60 mv turn off thre shol d du ring blankin g tim e (v ss -v d ) (5) 100 mv turn -off prop agation delay v d =v ss 15 ns t doff v d =v ss , c loa d =5nf, r ga t e =0 ? 60 120 ns turn-off, total delay t doff v d =v ss , c loa d =10n f, r gate =0 ? 60 120 ns pull down impeda nce 1 2 ? pull dow n cu rre nt (5) 3v MP6903- f a st turn-off intel l igent controll er MP6903 rev. 1. 04 www.monolithicpower.com 4 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. pin functio n s pin # nam e description 1 pgnd power ground. return for driver switch. 2 en enable. active high. 3 ll light load time set. connect a resistor to set the light load timing. 4 vd mosfet drain voltage sense. 5 vss ground. also used as reference for vd. 6 vdd supply voltage. 7 nc no connection. 8 vg gate drive output.
MP6903- f a st turn-off intel l igent controll er MP6903 rev. 1. 04 www.monolithicpower.com 5 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. typical perfo r manc e characteristics v dd = 12v, unless otherw ise noted . operation current vs. t emperature c load =5nf , f sw =100khz en uvlo rising vs. t emperature t urn on delay vs. t emperature c load =5nf light load mode current vs. t emperature en uvlo rising (v) v fwd vs. t e m p er at u r e - 50 0 50 100 150 v fwd (mv) tur n of f t hr e s hol d v s . t em p er at u r e -4 0 -3 5 -3 0 -2 5 -2 0 -50 0 50 100 150 tur n of f t h r e s hold ( v) q u i escen t c u r r en t vs. t e m p er at u r e 1 1. 2 1. 4 1. 6 1. 8 2 2. 2 2. 4 -50 0 50 100 150 q u i escen t cu r r en t ( ma ) 60 65 70 75 80 shutdown current v s . t em p er at u r e 50 100 150 200 -50 0 50 100 150 5 5. 5 6 6. 5 7 - 5 0 0 50 100 150 v dd uv l o ri s i n g ( v ) v dd uvlo rising v s . temperature 6.6 6.8 7 7.2 7.4 7.6 7.8 -50 0 50 100 150 opera tion current (ma) 250 270 290 310 330 350 -50 0 5 0 100 150 1.2 1.3 1.4 1.5 1.6 1.7 -50 0 5 0 100 150 0 100 200 300 400 500 600 700 -50 0 5 0 100 150 turn on dela y (ns)
MP6903- f a st turn-off intel l igent controll er MP6903 rev. 1. 04 www.monolithicpower.com 6 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. typical perfo r manc e characteristics (continued) v dd = 12v, unless otherwise noted. turn off delay (ns) t urn off delay vs. t emperature c load =5nf turn off delay vs. temperature c load =10nf turn-off threshold (5) vs. temperature minimum on t ime vs. t emperature turn on delay (ns) t urn on delay vs. t emperature c load =10nf 0 200 400 600 800 1,000 1,200 1,400 -50 0 50 100 150 0 10 20 30 40 50 60 70 80 90 -50 0 50 100 150 0 10 20 30 40 50 60 70 80 90 -50 0 50 100 150 turn off dela y (ns) 0.5 0.6 0.7 0.8 0.9 1.0 -50 0 5 0 100 150 1.5 1.6 1.7 1.8 1.9 2 -50 0 5 0 100 150 0 10 20 30 40 50 60 -50 0 5 0 100 150 turn-off threshold (5) (ns) v ds 20v/div v g 5v/div i sr 10a/div operation in llc resonant converter v in =250v, v out =12v, i out =15a dcm operation in llc resonant converter v in =263v, v out =12v, i out =15a crcm v ds 20v/div v g 5v/div i sr 10a/div operation in llc resonant converter v in =280v, v out =12v, i out =15a ccm v ds 20v/div v g 5v/div i sr 10a/div
MP6903- f a st turn-off intel l igent controll er MP6903 rev. 1. 04 www.monolithicpower.com 7 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. functional block diagram figure 1: functional block diagram operation the MP6903 supports operation in discontinuo us current mo de (dcm), continuous current mo de (ccm), an d critical conduction mode (crcm) condition. o perating in either a dcm or crcm condition, t h e control cir c uitry contro ls the gate in forward mo de and will t u rn the gate off when the mosfet current goes low. in ccm operation, the control circuitry turns off the gate when very fast transien t s occur. blanking the control circuitry con t ains a b l an king fun c tio n . when the mosfet turns on or of f, the blan king function e n sures that th e previous state extend s for some minimu m time period. the turn- on blanking t i me is ~0.8s. during the turn -on blanking p e r iod, the t u rn-off thre shold is n o t totally blan ked, but changes t he thresho l d voltage to approximatel y 100mv (in s tead of 0mv). this assure s that the part can always turn off even during the turn-o n blanking period. (th e synchronous period is recommended to b e greater than 0.8 s in c c m in the llc convert e r to avoid shoot-through.) vd clamp a high-volta ge jfet is used at the input because v d can go a s high a s 1 80v. to avoid excessive currents wh en v g goe s below -0.7v, add a sma ll resistor bet ween v d and the drain of the external mosfet. under-voltage lockout (uvlo) when v dd drops below the uvlo threshold, th e part goes into sleep mode and a 10k ? resist or pulls the v g pin low. enable pin en is intern al pulled up by the regulator from v dd with a ~15ua current source. leave this pin ope n if unused. when use external sig nal to cont rol en, it is highly recommended t he pull do wn current be larger than 15ua to make sure the en pin can be pulled to low .
MP6903- f a st turn-off intel l igent controll er MP6903 rev. 1. 04 www.monolithicpower.com 8 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. thermal shutdow n if the junction temperat ure of the chip exceeds 180c, the vg will be pulled low and the part stops switching. the part will resume normal function af t e r the jun c tion temp erature ha s dropped to 150c. turn-on ph ase when the synchronous mosfet is on, curre nt flows through its body diode and generates a negative v ds . this bod y diode voltage drop (< - 500mv) is much s m aller than the turn -on threshold of the control circuitry (-7 0mv), whic h then pulls th e gate drive r voltage high to turn o n the synchronous mosfet after about 250 ns turn-on dela y (shown in figure 2). when the tu rn-on delay ends, turn-o n starts with a blanking t i me (minimu m on-time: ~0.8s), and the turn-off threshold changes fro m +30mv t o +100mv. th is blanking time helps to avoid errors around the turn-off thre shold cau s e d by turn-on ringing of th e synchronous mosfet . figure 2: turn on/off timing diagram conducting phase when the synchronous mosf et turns on, v ds rises a ccord ing to the m o sfet?s on resistan c e . when v ds rises above the turn-on threshold (- 70mv), the control cir c u i try stops pulling up th e gate driver, so the gate voltage is pulled down by the internal pull-down resistance (10k ? ) and leakage to increase th e on resistance of th e synchronous mosfet, which to limit the v ds slew rate, stabilize s v ds to around -70mv e v e n when the current throu gh the mosfet is fairly small. this function limit s the driver voltage when the synchronous mosfet is turned off (this function i s st ill act i ve during turn-on blanking, which means the gate d r iver could still be turned - off even with very s m all duty cycles of t h e synchronous mosfet). turn-off ph ase when v ds triggers the t u rn-off threshold (30mv), the gate volt age is p u lle d to low afte r a 20ns tur n - off delay ( s hown in figure 2) by the con trol circuitry . figure 3 shows synchronous rectif icat ion operation at heavy load. the gate driver initially saturates d ue to the high current. after v ds rises above -70mv, the gate driver voltage decreases to adjust the v ds to around -70mv. figure 4 shows synchronous rectif icat ion operation at light load. the gate dr iver voltage never saturates due t o the low current, b u t decreases a s soon as th e synchrono us mosfet turns on and adjusts the v ds . figure 3: sy nchronou s rectification operation a t heav y lo ad figure 4: sy nchronou s rectification operation a t light load
MP6903- f a st turn-off intel l igent controll er MP6903 rev. 1. 04 www.monolithicpower.com 9 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. light-load latch-off f unction the gate driver of MP6903 is latched to save the driver loss at light-load condition to improve efficiency. see figure5, when the synchronous mosfet?s conducting period keeps lower than light load timing (t ll ) for longer than the light- load-enter delay (t ll-delay ), MP6903 enters light- load mode and latches off the gate driver. here the synchronous mosfet?s conducting period is from turn on of the gate driver to the moment when v gs drops to below 1v (v ll_gs ). secondary side current norm al mo de lig ht lo a d mod e t ll t ll t ll t ll- delay figure 5: MP6903 enters light load mode during light -load mode, MP6903 monitors th e synchronous mosfet? s body diod e conduct i n g period by sensing the time duratio n of the v ds below -250mv(v ll_ds ). if it is longer than t ll +t ll- h (t ll-h , ligh t -load-enter pulse widt h hysteresis), the light-loa d mode is finished and gate driver of MP6903 is unlatched to restart the synchronous rectificat ion, see figure6 . for mp690 3, the light load enter timing (t ll ) is programma ble by connecting a resistor (r ll ) on ll pin, by monitoring t he ll pin current (the ll pin voltage keeps at ~2 v internally), t ll is s e t as following (a 1nf capacitor is re co mmended t o decouple th e noise on t h is pin): ll ll 2.2 u s tr ( k ) 100 k ?? ? ? figure 6: MP6903 exits light load mode
MP6903- f a st turn-off intel l igent controll er notice: t he i n formatio n in this docum ent i s subject to chang e w i t h o u t notice. users sh oul d w a rra nt and gu arante e that third part y int e ll ectu al prop ert y r i g h ts are n o t inf r ing ed u p o n w hen i n tegr atin g mps product s into an y ap p licatio n. mps w i ll not assume a n y le gal res pons ib ili t y for an y sai d app licati ons. MP6903 rev. 1. 04 www.monolithicpower.com 10 1/31/2013 mps proprietar y information. pate nt protec ted. un authorized photo c op y and d uplication prohibited. ? 2013 mps. all rights reserved. package informati o n soic8 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0. 0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0 . 013(0 .33) 0 . 020(0 .51) seating plane 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.0 53(1.3 5) 0.069(1.75) top view front view 0.228(5.80) 0.244(6.20) side view 14 85 recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) note: 1) cont rol d i mension is in in ches. d imension in bra cket is in millimeter s . 2) pac kage len gt h does not in cl ude mold fl ash, protru sion s or ga te bu rrs. 3) pac kage width does not in clu de int e rlea d fl ash or protru sion s. 4) l e a d copla nar ity (bottom of l e ads a f t e r formin g ) shal l be 0 . 004" in ches max. 5) dr awing conf or ms to jedec ms-012, va riat ion aa. 6) dr awing is not to scale. 0.010(0.25) bsc gauge plane
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